The present invention relates to bus arbitration technology in an information processing device, and relates to technology effective when applied to, for example, a microcomputer (also referred to as microprocessor or data processor).
Patent Document 1 (Japanese Patent Laid-Open No. 1995-134689) describes technology to improve immediate responsiveness in bus arbitration. According to the technology, the bus arbiter and the unit coupled to the shared bus are coupled by a signal line and when there is a bus contention, a unit to be granted the use of the bus is determined based on the priority information sent to the signal line. By the bus arbiter itself being coupled to the shared bus, updating of information of priority order from the processor unit is enabled.
Patent Document 2 (Japanese Patent Laid-Open No. 2008-40650) describes technology to improve the performance of a system. According to the technology, in the bus arbitration device performing arbitration of access requests to the shared resource by a plurality of requestors via the shared bus, at least one of the requestors outputs an internal status signal to notify that the priority order of the access request by the requestor should be changed in accordance with the internal status. Then, the bus arbitration device performs arbitration of the access requests based on the internal status signal.
Patent Document 3 (Japanese Patent Laid-Open No. 2007-41771) describes technology to improve the unevenness of the use efficiency of the bus bandwidth. According to the technology, in the memory scheduler, the memory access totalization unit totalizes the use efficiency of the bus for each process ID from the memory access command and the bus use efficiency comparison unit compares the totalization result of the memory access totalization unit with the threshold value set in the threshold value setting unit. In accordance with the comparison result, the memory scheduler interrupts the process scheduler. The process scheduling change unit receives the interrupt from the memory scheduler and changes the process scheduling condition of the CPU core from the priority of the process to the use efficiency of the bus of the process.
Patent Document 4 (Japanese Patent Laid-Open No. 1992-250523) describes technology to increase the priority order of the process by software by selecting a specific window on the screen specified by a user.